library verilog;
use verilog.vl_types.all;
entity pmi_distributed_shift_reg_lossless is
    generic(
        pmi_data_width  : integer := 16;
        pmi_regmode     : string  := "reg";
        pmi_shiftreg_type: string  := "var";
        pmi_max_shift   : integer := 16;
        pmi_max_width   : integer := 4;
        pmi_init_file   : string  := "none";
        pmi_init_file_format: string  := "binary";
        pmi_family      : string  := "EC"
    );
    port(
        Din             : in     vl_logic_vector;
        Addr            : in     vl_logic_vector;
        Clock           : in     vl_logic;
        ClockEn         : in     vl_logic;
        Reset           : in     vl_logic;
        Q               : out    vl_logic_vector
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of pmi_data_width : constant is 1;
    attribute mti_svvh_generic_type of pmi_regmode : constant is 1;
    attribute mti_svvh_generic_type of pmi_shiftreg_type : constant is 1;
    attribute mti_svvh_generic_type of pmi_max_shift : constant is 1;
    attribute mti_svvh_generic_type of pmi_max_width : constant is 1;
    attribute mti_svvh_generic_type of pmi_init_file : constant is 1;
    attribute mti_svvh_generic_type of pmi_init_file_format : constant is 1;
    attribute mti_svvh_generic_type of pmi_family : constant is 1;
end pmi_distributed_shift_reg_lossless;
